In a prior art DPLL as shown in FIG. 1 the phase of a reference clock ref is sampled and converted to a digital phase value. A software digitally controlled oscillator (SDCO) is locked to the digital phase value. The SDCO controls the output of a hardware digitally controlled oscillator/voltage controlled oscillator (DCO/VCO) such that the frequency and phase of the DCO is synchronized with the SDCO. In this way, the output clock generated by the DCO/VCO is locked to the reference clock ref.
In many applications, it is a requirement that the output clock not only be synchronized to the reference clock, but also that its phase be aligned to the exact time reference. In a DPLL, the phase alignment of DCO/VCO output clock can be achieved by directly controlling the phase of the output clock with SDCO phase value as shown in FIG. 1.
The SDCO can control the DCO phase if both run on the same system clock. If there is any hardware delay in between the DCO and VCO, or in a VCO output pad, or in clock synthesis, such a hardware delay may cause the output clock to lose alignment with the reference clock.
In co-pending application Ser. No. 15/064,663, filed Mar. 9, 2016 and published as US 2016/0294401, the contents of which are herein incorporated by reference, it was shown that the hardware delay can be measured with a feedback path and the resulting delay compensated by adjusting the output clock with a pattern shifter.
The delay can be measured by averaging the phase delay between the sampled feedback output clock and the SDCO internal phase. The measured delay can then be compensated by adjusting the output pattern shifter as shown in FIG. 2. To get a good phase delay measurement, typically 50 to 100 clock samples are required. This can be a problem for a low frequency output. For example, in the case of a 1 Hz clock output, it means that the delay measurement can take 100 s. An even longer time is needed for output frequencies lower than 1 Hz. If the feedback channel is shared with multiple outputs, an even longer waiting time is needed if each output outputs the low frequency clock. Reducing the averaging average time will speed up the alignment procedure but with loss of alignment accuracy.